1. Field of the Invention
The present invention relates to a semiconductor device and a test method thereof, and more particularly relates to a semiconductor device including dummy word lines and a test method thereof.
2. Description of Related Art
The memory capacity required in memory devices such as DRAMs (Dynamic Random Access Memories) is increasing every year, and an area occupied by each memory cell to realize the increased memory capacity is steadily reducing. For example, a layout in which an area occupied by each memory cell is 6F2 has been known, where F is a minimum feature size (Japanese Patent Application Laid-open No. 2010-040131).
When the layout described in Japanese Patent Application Laid-open No. 2010-040131 is adopted, a dummy word line is arranged alternating with every two word lines. The dummy word line is a dummy wiring that essentially does not contribute to any actual operations, and is provided only to maintain a constant wiring density of a wiring layer in which the word lines and the dummy word lines are provided.
Because the dummy word line is the dummy wiring that essentially does not contribute to any actual operations as mentioned above, an electric potential of the dummy word line can be set arbitrarily, thereby the dummy word line can be set to be in a floating state. When the dummy word line is set to be in a floating state, because there is no need to supply a predetermined electric potential to the dummy word line, an element such as a wiring or a connector is not required for the dummy word line. Therefore, there is an advantage that overhead in terms of area does not occur in an area where word line drivers are formed.
However, because the electric potential of the dummy word line becomes unstable when it is set to be in a floating state, the dummy word line is likely to become a noise source for neighboring elements or wirings. To prevent this problem, one approach is to supply a predetermined electric potential to the dummy word line. However, in this case, if there is a short circuit or minute current leakage between the word line and the dummy word line, a leakage current flows between the word line and the dummy word line, making the word line defective and creating a need to replace the defective word line with an auxiliary word line. In this case, because a certain length of time needs to be spent to specifically detect the word line defect caused by the minute current leakage to the dummy word line, there is a problem that the time necessary for an operation test at a manufacturing stage becomes longer.
This problem is not limited to DRAMs, but also occurs in other memory devices (such as SRAM, PRAM, MRAM, FeRAM, and ReRAM) in which dummy word lines are provided adjacent to word lines or in all semiconductor devices including some circuits similar to such memory devices.